Field of the Disclosure
The present disclosure relates generally to processors and more particularly to adaptive voltage and frequency scaling for processors.
Description of the Related Art
The operational speed of a processor is limited by the propagation delay along circuit paths between input and output nodes of the processor. The period of a clock signal used to synchronize processor operations must be long enough to allow input signals to propagate along the circuit paths so that corresponding output nodes reach their responsive states before the end of each clock cycle. If the delay introduced by a circuit path is too long, an input signal may not produce the correct output state at the corresponding output node. Accordingly, the maximum clock frequency to ensure correct operation of the processor at a specified supply voltage is typically governed by the circuit paths having the largest delays. Such circuit paths are sometimes referred to as critical paths. Conventionally, the maximum clock frequency and corresponding supply voltage for the processor are determined by applying test patterns to the circuit paths of one or more test chips at varying clock frequencies and comparing resulting signals at the output nodes to expected signals. However, because of the large number of circuit paths in modern processors, such testing can be expensive and time consuming. In addition, to ensure proper operation of the largest number of processors, the maximum clock frequency and supply voltage are typically set to the “worst-case” values established during testing. Because of variations in process and operating conditions, the critical paths of the test chips may vary from the critical paths of a given processor, and the worst-case values may be too conservative for that processor, unnecessarily limiting processor performance.